Thomas Vogelsang

Thomas Vogelsang

Thomas
Vogelsang

Publications

International Memory Workshop

May 2018

DRAM Retention at Cryogenic Temperatures

Journal of Electronic Imaging

April 2018

Optimization of CMOS image sensor utilizing variable temporal multisampling partial transfer technique to achieve full-frame high dynamic range with superior low light and stop motion capability

Electronic Imaging

February 2017

Optimization of CMOS image sensor utilizing variable temporal multi-sampling partial transfer technique to achieve full-frame high dynamic range with superior low light and stop motion capability

International Symposium on Circuits and Systems

May 2017

Reducing electrical power dissipation in computational imaging systems through special-purpose optics

Electronic Imaging

February 2017

Optimization of CMOS image sensor utilizing variable temporal multi-sampling partial transfer technique to achieve full-frame high dynamic range with superior low light and stop motion capability

COSI

July 2016

Optical Performance of Computational Diffractive Imagers

VLSI Symposium

June 2016

Lensless Smart Sensors: Optical and Thermal Sensing for the IoT

Sensors Magazine

April 2016

Reduction of CMOS Image Sensor Read Noise to Enable Photon Counting

IISW

June 2015

A 2MP Oversampling Image Sensor with 2.75μs Row Time and Conditional Threshold Comparison

COSI

June 2015

Computational Diffractive Imager with Low-Power Image Change Detection

ISCE

June 2014

Non-Destructive Threshold Assessment of a Pinned Photo Diode Pixel with Correlated Double Sampling

JEI

January 2014

Hardware Validated Unified Model of Multibit Temporally and Spatially Oversampled Image Sensors with Conditional Reset

ICIP

August 2013

Multichannel Sampling of Low Light Level Scenes with Unknown Shifts

IISW

June 2013

Overcoming the Full Well Capacity Limit: High Dynamic Range Imaging Using Multi-Bit Temporal Oversampling and Conditional Reset

IEEE Sensors Conference

October 2012

High-Dynamic-Range Binary Pixel Processing Using Non-Destructive Reads and Variable Oversampling and Thresholds

Micro

December 2010

Understanding the Energy Consumption of Dynamic Random Access Memories

JSSCC

January 2005

A 3.6-Gb/s Point-to-Point Heterogeneous-Voltage-Capable DRAM Interface for Capacity-Scalable Memory Subsystems

ISSCC

February 2004

A 2Gb/s Point-to-Point Heterogeneous Voltage Capable DRAM Interface for Capacity-Scalable Memory Subsystems

VLSI Symposium

June 2002

A 110nm 512Mb DDR DRAM with Vertical Transistor Trench Cell

SSDM

September 1994

Modelling and Fabrication of a P-Channel SiGe-MOSFET with Very High Mobility and Transconductance

TED

September 1994

A Comparison of Numerical Solutions of the Boltzmann Transport Equation for High-Energy Electron Transport Silicon

APL

July 1993

Electron Transport in Strained Si Layers on Si1-xGx substrates

TED

November 1992

Electron Mobilities and High-Field Drift Velocities in Strained Silicon on Silicon-Germanium Substrates

JAP

August 1991

A Novel Approach for Including Band-Structure Effects in a Monte Carlo Simulation of Electron Transport in Silicon

ESSDERC

September 1989

Charge transport near the Si/SiO2 Interface in MOSFET Devices

Patents

US 10,136,090 B2

Threshold Monitoring, Conditional-Reset Image Sensor

US 10,104,318 B2

High Dynamic-Range Image Sensor

US 10,070,084 B2

Image Sensor with Multi-Range Readout

US 9,983,830 B2

Memory Component Having Internal Read Modify-Write Operation

US 9,911,468 B2

Memory with Deferred Fractional Row Activation

US 9,894,304 B1

Line Interleaved Image Sensors

US 9,875,787 B2

Reduced Transport Energy in a Memory System

US 9,826,176 B1

Shared Counter Image Sensor

US 9,691,504 B2

DRAM Retention Test Method for Dynamic Error Correction

US 9,681,071 B2

Image Sensor with Exception Coded Output Compression

US 9,667,898 B2

Conditional Reset, Multi-Bit Read-Out Image Sensor

US 9,666,238 B2

Stacked DRAM Device and Method of Manufacture

US 9,575,835 B2

Error Correction in a Memory Device

US 9,570,196 B2

Testing Through-Silicon-Vias

US 9,570,144 B2

Memory Refresh Method and Devices

US 9,570,126 B2

Memory with Deferred Fractional Row Activation

US 9,548,102 B2

Multi-die DRAM Banks Arrangement and Wiring

US 9,521,351 B1

Fractional Readout Oversampled Image Sensor

US 9,521,349 B2

Image Sensor Architecture with Power Saving Readout

US 9,521,338 B2

Image Sensor Sampled at Non-Uniform Intervals

US 9,515,008 B2

Techniques for Interconnecting Stacked Dies Using Connection Sites

US 9,491,391 B2

Image Sensor with Threshold-Based Output Encoding

US 9,438,826 B2

Pixel Structure and Reset Scheme

US 9,437,280 B2

DRAM Sense-Amplifier that Supports Low Memory-Cell Capacitance

US 9,432,597 B2

Low-Noise High Dynamic-Range Image Sensor

US 9,411,678 B1

DRAM Retention Monitoring Method for Dynamic Error Correction

US 9,380,245 B1

Conditional-Reset Image Sensor with Analog Counter Array

US 9,361,960 B2

Configurable Memory Banks of a Memory Device

US 9,344,635 B2

Conditionally-Reset, Temporally Oversampled Image Sensor

US 9,330,735 B2

Memory with deferred fractional row activation

US 9,287,239 B2

Techniques for Interconnecting Stacked Dies Using Connection Sites

US 9,286,965 B2

Memory Refresh Method and Devices

US 9,264,639 B2

Feedthrough-Compensated Image Sensor

US 9,256,376 B2

Methods and Circuits for Dynamically Scaling DRAM Power and Performance

US 9,214,219 B2

Distributed Sub-Page Selection

US 9,116,781 B2

Memory Controller and Memory Device Command Protocol

US 9,111,588 B2

Multi-Die DRAM Banks Arrangement and Wiring

US 9,037,949 B1

Error Correction in a Memory Device

US 9,036,065 B1

Shared-Counter Image Sensor

US 9,001,606 B2

Memory Methods and Systems with Adiabatic Switching

US 9,001,251 B2

Oversampled Image Sensor with Conditional Pixel Read-Out

US 8,982,598 B2

Stacked Memory Device with Redundant Resources to Correct Defects

US 8,930,779 B2

Bit-Replacement Technique for DRAM Error Correction

US 8,908,454 B2

Memory Architecture with Redundant Resources

US 8,885,423 B2

DRAM Sense-Amplifier that Supports Low Memory-Cell Capacitance

US 8,811,095 B2

Methods and Circuits for Dynamically Scaling DRAM Power and Performance

US 8,717,797 B2

Semiconductor Memory Device with Hierarchical Bitlines

US 8,473,808 B2

Semiconductor Memory Having Non-Standard Form Factor

US 7,956,644 B2

Peak Power Reduction using Fixed Bit Inversion

US 7,937,631 B2

Method for Self-Test and Self-Repair in a Multi-Chip Package Environment

US 7,797,511 B2

Memory Refresh System and Method

US 7,440,347 B1

Circuit and Method to Find Wordline-Bitline Shorts in a DRAM

US 7,375,999 B2

Low Equalized Sense-Amp for Twin Cell DRAMs

US 7,342,291 B2

Standby Current Reduction over a Process Window with a Trimmable Well Bias

US 7,333,383 B2

Fuse Resistance Readout Circuit

US 7,293,190 B2

Noisy Clock Test Method and Apparatus

US 7,254,089 B2

Memory with Selectable Single Cell or Twin Cell Configuration

US 7,227,799 B2

Sense Amplifier for Eliminating Leakage Current due to Bit Line Shorts

US 7,060,566 B2

Standby Current Reduction over a Process Window with a Trimmable Well Bias

US 7,060,529 B2

Multiple Chip Semiconductor Arrangement Having Electrical Components in Separating Regions

US 6,815,803 B1

Multiple Chip Semiconductor Arrangement Having Electrical Components in Separating Regions

US 6,813,193 B2

Memory Device and Method of Outputting Data from a Memory Device

US 6,730,989 B1

Semiconductor Package and Method

US 6,369,606 B1

Mixed Threshold Voltage CMOS Logic Device and Method for Manufacture Thereof

US 6,160,747

Configuration for Crosstalk Attenuation in Word Lines of DRAM Circuits

US 6,067,261

Timing of Wordline Activation for DC Burn-In of a DRAM with the Self-Refresh

US 6,049,492

Integrated Sense-Amplifier with a Single-Sided Precharge Device

US 5,612,233

Method for Manufacturing a Single Electron Component

US 5,559,353

Integrated Circuit Structure Having at Least One CMOS NAND Gate and Method for the Manufacture Thereof

US 5,540,977

Microelectronic Component

US 5,443,992

Method for Manufacturing an Integrated Circuit Having at Least One MOS Transistor.